1. Field of Invention
This invention relates generally to digital circuits and specifically to dynamic flip-flops.
2. Description of Related Art
Dynamic logic gates operate in two phases: a pre-charge phase and an evaluation phase. During the pre-charge phase, the dynamic logic gate drives its output terminal to a first logic state. Then, during the evaluation phase, the dynamic logic gate causes its output signal to either remain at the first logic state or transition to a second logic state, depending upon the dynamic logic gates' input signal(s). The dynamic logic gate returns its output signal to the first logic state during the next pre-charge phase. By forcing its output signal to the same logic state prior to each evaluation phase, the dynamic logic gate need only allow logic transitions in one direction during the evaluation phase. As a result, the dynamic logic gate may be optimized to favor logic transitions from the first logic state to the second logic state during the evaluation phase, which in turn improves performance over static logic gates which allow logic transitions in both directions, and thus cannot be optimized for logic transitions in one direction.
In the past, static flip-flops were typically used to drive dynamic logic gates. However, in addition to allowing logic transitions in both directions, a static flip-flop provides an output signal that requires a certain amount of time to become stable, and therefore must be synchronized with the two-phase operation of dynamic logic gates. The time and uncertainty involved in synchronizing the output signal of a static flip-flop with the input signal requirements of a dynamic logic gate undesirably limits the performance of dynamic logic.
More recently, a dynamic flip-flop was disclosed in U.S. Pat. No. 5,825,224 issued to Klass and assigned to the assignee of the present invention, that eliminates the time penalty associated using static flip-flops to drive dynamic logic gates. FIG. 1 is a block diagram of a dual-rail dynamic flip-flop 10 of the type disclosed in U.S. Pat. No. 5,825,224, which is incorporated by reference herein. The dynamic flip-flop 10 includes a first input latch 11 with a shut-off circuit 12, a second input latch 13 with a shut-off circuit 14, and output latches 15 and 16. The first and second input latches 11 and 13 are clocked with a clock signal CLK. The first input latch 11 receives a data signal D, and in response thereto provides an output signal to the first output latch 15 via node OUT1. The second input latch 13 receives complementary data signal D via inverter INV1, and in response thereto provides an output signal to the second output latch 16 via node OUT2N. The shut-off circuit 12 prevents the first input latch 11 from further sampling signal D when output node OUT2N transitions to logic low, and the shut-off circuit 14 disables the second input latch 13 from further sampling signal D when output node OUT1 transitions to logic low. Together, the shut-off circuits 12 and 14 implement edge-triggered data sampling for the dual evaluation paths on node OUT1 and OUT2N, respectively.
Referring also to FIG. 2, when the clock signal CLK is logic low, the dynamic flip-flop circuit 10 is in the pre-charge phase. The input latches 11 and 13 pre-charge their respective output nodes OUT1 and OUT2N to logic high. The logic high level at node OUT1 is inverted by output latch 15, which in turn drives the Q output signal to logic low. The logic high level at node OUT2N is inverted by output latch 16, which in turn drives the Q output signal to logic low. On the rising edge of CLK, the dynamic flip-flop 10 enters the evaluation phase. The first input latch 11 samples the data signal D and, in response thereto, causes its output node OUT1 to either remain logic high or to transition to logic low. The output latch 15 inverts the logic state at node OUT1 to generate the Q output signal. Similarly, the second input latch 13 samples the complementary data signal D and, in response thereto, causes its output node OUT2N to either remain logic high or to transition to logic low. The output latch 16 inverts the logic state at node OUT2N to generate the Q output signal.
FIG. 3 is a schematic diagram of the dynamic flip-flop circuit 10 disclosed in U.S. Pat. No. 5,825,224. The first input latch 11 includes p-channel transistors PC1 and K2, n-channel transistors S1 and N1, and inverters INV2 and INV3, where the transistor S1 and inverters INV2 and INV3 implement the shut-off circuit 12. The second input latch 13 includes p-channel transistors K1 and PC2, n-channel transistors S2 and N2, and inverters INV4 and INV5, where the transistor S2 and inverters INV4 and INV5 implement the shutoff circuit 14. The input latches 11 and 13 share an n-channel transistor EVAL. The first input latch 11 receives the data signal D at the gate of its input transistor N1, and the second input latch 13 receives the complemented data signal D via inverter INV1 at the gate of its input transistor N2. The output latch 15 includes an inverter INV6 and a n-channel transistor N3, and the output latch 16 includes an inverter INV7 and a n-channel transistor N4.
During the pre-charge phase, the logic low CLK signal turns off the evaluation transistor EVAL and turns on the pre-charge transistors PC1 and PC2. With the non-conducting evaluation transistor isolating nodes OUT1N and OUT2N from the low voltage rail (e.g., ground potential), the pre-charge transistors PC1 and PC2 quickly pre-charge respective nodes OUT1N and OUT2N toward the V.sub.DD rail. The resultant logic high levels at nodes OUT1N and OUT2N propagate through respective inverters INV6 and INV7, which in turn cause respective Q and Q output signals to be logic low during the pre-charge phase (see the timing diagram of FIG. 2). The logic high levels at nodes OUT1N and OUT2N maintain respective p-channel keeper transistors K1 and K2 in a non-conducting state, and also turn on respective shut-off transistors S1 and S2.
When the clock signal CLK transitions to logic high, the evaluation transistor EVAL turns on and discharges node CGND to logic low, thereby commencing the evaluation phase. The logic high clock CLK also turns off the pre-charge transistors PC1 and PC2. If the data signal D is logic high when the evaluation phase begins, the first input transistor N1 turns on while the second input transistor N2 turns off. Output node OUT1N discharges to logic low through transistors S1, N1 and EVAL, while the non-conducting input transistor N2 maintains output node OUT2N at logic high. The inverter INV6 inverts the logic low level at node OUT1N to drive the Q output signal to logic high, and the inverter INV7 inverts the logic high level at node OUT2N to keep the Q output signal at logic low. The logic low level at node OUT1N turns off the shut-off transistor S2 via inverters INV4 and INV5 to prevent the second input latch 13 from further data sampling. The logic low signal at node OUT1N also turns on transistor K1, which maintains node OUT2N at logic high to reduce charge loss.
Conversely, if the data signal D is logic low, the input transistor N1 turns off and thus does not discharge node OUT1N toward ground potential. The resulting logic high signal at node OUT1N is inverted by INV6 to drive the Q output signal to logic low. The logic low data signal D is inverted by INVL to generate a logic high complementary data signal D, which turns on the second input transistor S2 to discharge the second output node OUT2N to logic low. In response thereto, the output latch 16 drives its Q output signal to logic high, as illustrated by the dashed Q waveform in FIG. 2. The logic low signal at node OUT2N turns off the shut-off transistor S2 via inverters INV3 and INV2 to prevent the first input latch 11 from further data sampling.
Although effective in eliminating the static flip-flop time penalty discussed above by providing Q and Q output signals that are compatible with dynamic logic, the complementary evaluation paths of the dynamic flip-flop circuit undesirably require duplicate circuitry. For example, sampling the data signal D to generate the Q output signal via node OUT1N and sampling the complementary data signal D to generate the Q output signal via node OUT2N requires two latches 11 and 13, and thus two evaluation paths, two shut-off circuits 12 and 14, and so on. Requiring duplicate circuitry undesirably increases circuit size and complexity, which in turn increases power consumption.
Further, using dual evaluation paths to generate dynamic logic-compatible output signals undesirably restricts implementation of multi-input logic functions in a dynamic flip-flop. For example, FIG. 4 shows the flip-flop circuit 10 modified to implement a 4-input logic AND function. Each of the input signals D0-D3 requires a corresponding series-connected input transistor N1 in the first input latch 11 to participate in the generation of the Q output signal, and also requires a corresponding parallel-connected input transistor N2 in the second input latch 13 to participate in the generation of the Q output signal. The series-connected input transistors N1(0)-N1(3) discharge node OUT1N toward ground potential, which in turn drives the Q output signal to logic high, only when all input signals D0-D3 are logic high to implement the AND logic function Q=D0.cndot.D1.cndot.D2.multidot.D3, where .cndot.0 is the logic AND function. For the complementary evaluation path, any one of the parallel-connected input transistors N2(0)-N2(3) may discharge node OUT2NN toward ground potential, which in turn drives the Q output signal to logic high, when any of the complementary input signals D0-D3 are logic high. This implements the complementary evaluation path of Q=D0+D1+D2+D3, where + is the logic OR function.
Implementation of multiple-input logic functions using dual evaluation paths significantly increases circuit complexity and silicon area, since each input signal requires two input transistors N1(x) and N2(x) and an inverter INV1. Further, since each of the series-connected input transistors N1(0)-N1(3) increases the resistance of the discharge path from node OUT1N to ground potential, which in turn increases the time required to discharge node OUT1N, increasing the number of input signals undesirably degrades circuit performance. This results in an undesirable trade-off between the number of input signals and circuit performance. Accordingly, there is a need for a simpler dynamic flip-flop circuit that can also implement multiple-input logic functions without sacrificing circuit performance.